1. Field of the Invention
The present invention relates to a method for fabricating a capacitor, and more particularly, to a method for fabricating a capacitor for a semiconductor device. While the capacitor of the present invention is suited for a variety of applications, it is particularly suited for semiconductor DRAMs.
2. Discussion of the Related Art
Generally, as the packing density of a semiconductor device increases, the area of a capacitor of the semiconductor device becomes reduced, resulting in a capacitance reduction. In order to compensate for the reduced capacitance, the capacitor dielectric layer becomes thinner. However, as the thickness of the dielectric layer decreases, the leakage current due to tunneling increases. As a result, the reliability of the semiconductor device deteriorates.
In order to keep the dielectric layer from becoming too thin while maintaining its capacitance, a widely used method forms a capacitor with a rough surface to thereby increase the effective area of the capacitor. Another method is to use a nitride oxide layer or reoxidized nitride oxide layer having a high dielectric constant as a dielectric layer for the capacitor. However, these methods produce steps or unevenness on the surface of a semiconductor device making it difficult to apply a photolithography process. This in turn increases the production cost. Accordingly, it is difficult to apply there methods to highly integrated devices such as 256M DRAMs.
To increase the capacitance of a capacitor while reducing its surface roughness, one method is to use a material with a high dielectric constant as the dielectric layer for the capacitor. Accordingly, many studies concerning this technology have been performed. To date, the most widely studied material having a high dielectric constant is Ta.sub.2 O.sub.5. A dielectric layer made of this material has several advantages such as thinning of the dielectric layer and improvement of the characteristics of the device. However, since the substantial dielectric constant of Ta.sub.2 O.sub.5 is not very high, it will not be adequate for the new generations of highly integrated devices considering the trend of continual increase in packing density in the industry.
Recently, a perovskite-type oxide, such as a ferroelectric material, has become the center of studies as a dielectric to be used in semiconductor devices. The perovskite-type oxide includes Pb(Zr,Ti)O.sub.3 (PZT), (Pb,La) (Zr,Ti) O.sub.3 (PLZT), (Ba,Sr)TiO.sub.3 (BST), BaTiO.sub.3, and SrTiO.sub.3. However, these materials easily react with silicon and silicide which form substrates. In addition, a strong oxidizing ambient is required during the formation of a thin film of those materials when oxidizing the electrode of the capacitor. Accordingly, studies to solve these fabrication-related problems have been carried out.
To form a conventional capacitor, after the formation of an electrode having a complicated structure, an oxide layer is usually formed on the surface of the electrode. Hence, there is no step coverage problem. Since the perovskite material includes various constituent elements, it is difficult to form a good quality perovskite film by oxidizing the electrode. Thus, it is often formed by using a chemical vapor deposition (CVD) method. Metal organic compounds may be used as a reaction source (including the required elements) for forming the perovskite film in a CVD method. Therefore, it is possible to fabricate a dielectric thin film through a metal organic chemical vapor deposition (MOCVD) method where the thin film is formed of metal organic compounds. Given its good step coverage, the CVD method is capable of depositing a material on a considerably uneven or rough surface of a substrate or in small holes. However, the CVD method is not suitable for forming a device having very small and deep holes.
Conventional capacitor structures for semiconductor devices and methods for fabricating the same will now be explained with reference to the accompanying drawings. FIGS. 1 and 2 are cross-sectional views of a conventional capacitor structure for semiconductor devices.
As shown in FIG. 1, an interlevel insulating layer 2 is formed on a substrate 1 on which a transistor (not shown) is formed, and a material for forming an electrode 3 is deposited on the interlevel Insulating layer 2. Then, the material is selectively removed through photolithography to form the electrode 3, and a dielectric layer 4 is formed on the overall surface of the electrode 3. However, if the dielectric layer 4 is formed to maintain its thickness on the overall surface of the substrate to a predetermined minimum thickness, the dielectric layer 4A becomes thicker on the horizontal surface of the electrode 3 than on the portion 4B where the electrode 3 was selectively removed. This is caused by a poor step coverage around small gaps, where the material for the electrode is selectively removed. Accordingly, a substantial capacitance is reduced.
Furthermore, the electrode 3 has a vertical surface at its edge so that a rectangular protrusion is formed at the portion where the horizontal surface and the vertical surface meet. Accordingly, the characteristics of the dielectric layer 4B formed on the rectangular protrusion portion become poor since the electric field is concentrated on the protrusion portion. This results in leakage current or deterioration of the device.
In an attempt to solve the above problem, U.S. Pat. No. 5,335,138 discloses a method in which sidewalls 5 are formed around the electrode 3 to remove the sharp protrusion portion, as shown in FIG. 2. However, if the sidewalls 5 are formed of a conductive material, the dielectric layer 4 will be formed nonuniformly. On the other hand, if the sidewalls 5 are formed of an insulative material, a substantial area of the electrode will be reduced. In addition, the number of depositing and etching processes increase to thereby raise the production cost.
Problems also arise when an MOCVD method is used to form the dielectric layer 4. Because a reaction source having a low steam pressure has to be used, the process is complicated. Moreover, since MOCVD has not been widely applied to actual production processes, it may have many unknown and unexpected problems.
The aforementioned problems can be solved by using a sputtering technique where a target with a well-adjusted constitution is used. This facilitates the adjustment of the constitution of the dielectric layer. In addition, since the sputtering technique has been widely used in the fabrication of semiconductor, it in easy to cope with any potential problems because such problems are more predictable. But on the other hand, since it is hard to carry out a conformal deposition by sputtering, it is difficult to apply sputtering to the fabrication of high-integration devices.
FIG. 3 is a cross-sectional view of a third conventional capacitor structure for a semiconductor device disclosed by Shinkawata et al. in "The 42nd Spring Meeting Extended Abstracts," The Japan Society of Applied Physics and Related Societies, p. 789, 1995. In this capacitor structure, a planarized electrode structure is formed and a dielectric layer is then formed using sputtering.
Referring to FIG. 3, a first insulating layer 12 is formed on a substrate 11, on which a transistor is formed (not shown). A lower electrode 13A is formed on the first insulating layer 12 and buried in a second insulating layer 14. A dielectric layer 15 is formed on the overall surface of the second insulating layer 14 and the lower electrode 13A. An upper electrode 16 is formed on the dielectric layer 15.
FIGS. 4a to 4d are cross-sectional views showing the fabricating process of the conventional capacitor of FIG. 3. As shown in FIG. 4a, a first insulating layer 12 is formed on a substrate 11, on which a transistor is formed (not shown). Next, a material 13 for forming an electrode is deposited on the first insulating layer 12. As shown in FIG. 4b, the material 13 is then selectively removed through photolithography to form a lower electrode 13A, and a second insulating layer 14 is formed on the lower electrode 13A and the first insulating layer 12. Here, the second insulating layer 14 is formed of silicon oxide.
As shown in FIG. 4c, the second insulating layer 14 is selectively removed by using chemical mechanical polishing (CMP) to expose the lower electrode 13A. Then, as shown in FIG. 4d, a dielectric layer 15 and an upper electrode 16 are sequentially formed on the lower electrode 13A and the second insulating layer 14.
However, this conventional method forms the electrode through photolithography, it is difficult to use this method with a material such as Pt. Even though Pt is one of the most widely used material for forming ferroelectric capacitors, it is difficult to etch, thus unsuitable for conventional methods.